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Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM PIN CONFIGURATION
DESCRIPTION
The MH8V725BAZTJ is 8388608-word x 72-bit dynamic ram module. This consist of nine industry standard 8M x 8 dynamic RAMs in TSOP and three industry standard input buffer in TSSOP. The mounting of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module.
85pin 94pin
1pin 10pin 11pin
FEATURES
Type name
MH8V725BAZTJ-5 MH8V725BAZTJ-6
/RAS /CAS Address /OE access access access access time time time time Cycle time Power dissipation
(typ.W) (max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
95pin
50 60
18 20
30 35
18 20
90 110
2.80 2.35
Utilizes industry standard 8M x 8 RAMs in TSOP and industry standard input buffer in TSSOP 168-pin (84-pin dual dual in-line package) Single +3.3V(0.3V) supply operation Low stand-by power dissipation 116.2mW(Max) . . . . . . . . . . LVCMOS input level Low operation power dissipation MH8V725BAZTJ -5 . . . . . . . . . . . . . . . . . . 3.34W(Max) MH8V725BAZTJ -6 . . . . . . . . . . . . . . . . . . 3.02W(Max) All input are directly LVTTL compatible All output are three-state and directly LVTTL compatible Includes(0.22uF x 11) decoupling capacitors 4096 refresh cycle every 64ms (A0~12) Hyper-page mode,Read-modify-write, /CAS before /RAS refresh,Hidden refresh capabilities JEDEC standard pin configuration & Buffered PD pin Buffered input except /RAS and DQ Gold plating contact pads
124pin BACK SIDE 125pin
40pin FRONT SIDE 41pin
APPLICATION
Main memory unit for computers , Microcomputer memory 168pin 84pin
PD&ID TABLE
-5 -6 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 0 0 0 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0
1 = NC , 0 = drive to VOL PD pin . . . buffered. When /PDE is low, PD information can be read ID pin . . . non-buffered
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 1 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Pin No.
PIN CONFIGURATION
Pin No.
Pin Name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 DQ16 DQ17 Vss Reserved Reserved Vcc /WE0 /CAS0 Reserved /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 A12 Vcc RFU RFU
Pin Name Vss /OE2 /RAS2 /CAS4 Reserved /WE2 Vcc Reserved Reserved DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 Vss DQ28 DQ29 DQ30 DQ31 Vcc DQ32 DQ33 DQ34 DQ35 Vss PD1 PD3 PD5 PD7 ID0 Vcc
Pin No.
Pin Name Vss DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 Vss DQ45 DQ46 DQ47 DQ48 DQ49 Vcc DQ50 DQ51 DQ52 DQ53 Vss Reserved Reserved Vcc RFU Reserved Reserved Reserved RFU Vss A1 A3 A5 A7 A9 A11 Reserved Vcc RFU B0
Pin No.
Pin Name Vss RFU Reserved Reserved Reserved /PDE Vcc Reserved Reserved DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 Vss DQ64 DQ65 DQ66 DQ67 Vcc DQ68 DQ69 DQ70 DQ71 Vss PD2 PD4 PD6 PD8 ID1 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Reserved: Reserved use RFU: Reserved for future use
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 2 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
/RAS2 /CAS4 /WE2 /OE2
/OE /W /CAS /RAS
BLOCK DIAGRAM
/RAS0 /CAS0 /WE0 /OE0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
/OE /W /CAS /RAS
D0
DQ1 ~DQ8
D5
DQ1 ~DQ8
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71
/OE /W /CAS /RAS
/OE /W /CAS /RAS
D1
DQ1 ~DQ8
D6
DQ1 ~DQ8
/OE /W /CAS /RAS
/OE /W /CAS /RAS
D2
DQ1 ~DQ8
D7
DQ1 ~DQ8
/OE /W /CAS /RAS
/OE /W /CAS /RAS
D3
DQ1 ~DQ8
D8
DQ1 ~DQ8
/OE /W /CAS /RAS
D4
DQ1 ~DQ8
D : M5M465805BTP
D0~D4 D5~D8 D0~D8
PIN NAME /RAS /CAS /WE /OE A, B DQ Vcc Vss FUNCTION ROW ADDRESS STROBE INPUT COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT OUTPUT ENABLE INPUT ADDRESS INPUT DATA I/O POWER SUPPLY GROUND
A0 B0 A1~A12 MIT-DS-0285-0.0
Vcc Vss
C1~C11 ...
D0~D8 & INPUT BUFFER
MITSUBISHI ELECTRIC
( 3 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
a number of other functions, e.g., Hyper page mode, /CAS before /RAS refresh, and delayed-write. The input conditions for each are shown in Table 1.
FUNCTION
The MH8V725BAZTJ provide, in addition to normal read, write, and read-modify-write operations,
Table 1 Input conditions for each mode
Inputs Operation /RAS Read Write (Early write) Write (Delayed write) Read-modify-write Hidden refresh /CAS before /RAS refresh Standby ACT ACT ACT ACT ACT ACT NAC /CAS ACT ACT ACT ACT ACT ACT DNC /W NAC ACT ACT ACT DNC NAC DNC /OE ACT DNC DNC ACT ACT DNC DNC Row address APD APD APD APD DNC DNC DNC Column address APD APD APD APD DNC DNC DNC Input/Output Refresh Input OPN VLD VLD VLD OPN DNC DNC Output VLD OPN IVD VLD VLD OPN OPN NO NO NO NO YES YES NO Hyper page mode identical Remark
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 4 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Conditions With respect to Vss Ta=25C Ratings -0.5~ 4.6 50 10.7 0~70 -40~100 Unit V mA W C C
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc IO Pd Topr Tstg Parameter Supply voltage Output current Power dissipation Operating temperature Storage temperature
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage Min 3.0 0 2.0 -0.3
(Ta=0~70C, unless otherwise noted) (Note 1)
Limits Nom Max 3.3 3.6 0 0
Vcc+0.3
Unit V V V V
0.8
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol VOH VOL IOZ II I I (RAS) Parameter
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions IOH=-2.0mA IOL=2.0mA Q floating 0V VOUT Vcc
0VVINVcc+0.3, Other input pins=0V 0VVINVcc+0.3, Other input pins=0V
High-level output voltage Low-level output voltage Off-state output current Input current (except /RAS) Input current (/RAS) Average supply ICC1 (AV) current from Vcc operating ICC2
Min 2.4 0 -10 -10 -90
Limits Max Typ Vcc 0.4 10 10 90 920 830 29 24.5 920
Unit V V uA uA uA mA
-5 -6
(Note 3,4,5)
/RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open
/RAS=/CAS=WEVcc -0.2, output open
Supply current from Vcc , stand-by Average supply current from Vcc Hyper-Page-Mode
mA mA
-5 -6 -5 -6
ICC4(AV)
(Note 3,4,5)
/RAS=VIL,/CAS cycling tPC=min. output open /CAS before /RAS refresh cycling tRC=min. output open
830 1190 mA 1100
ICC6(AV)
Average supply current from Vcc /CAS before /RAS refresh (Note 3,5) mode
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column address can be changed once or less while /RAS=VIL and /CAS=VIH
CAPACITANCE
Symbol
(Ta = 0~70C, Vcc = 3.3V0.3V, Vss = 0V, unless otherwise noted)
Parameter
Test conditions VI=Vss f=1MHZ Vi=25mVrms
Min
Limits Typ
CI (/RAS) Input capacitance, /RAS input CI Input capacitance, except /RAS input C(DQ) Input/Output capacitance,DATA
Max 45 20 22
Unit pF pF pF
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 5 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
SWITCHING CHARACTERISTICS
Symbol tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ
Limits Parameter Min Access time from /CAS Access time from /RAS Column address access time Access time from /CAS precharge Access time from /OE Output hold time from /CAS Output hold time from /RAS Output low impedance time /CAS low Output disable time after /OE high Output disable time after /WE high Output disable time after /CAS high Output disable time after /RAS high
(Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 13) (Note 7) (Note 12) (Note 12) (Note 12,13) (Note 12,13)
-5 Max 18 50 30 33 18 Min
-6 Max 20 60 35 38 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns
10 5 10 18 18 18 13
10 5 10 20 20 20 15
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing /CAS before /RAS refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA). The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL). 8: Assumes that tRCD tRCD(max), tASC tASC(max) and tCP tCP(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT I 10uA I ) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both /RAS and /CAS go to high.
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70C, Vcc=3.3V0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Limits Symbol tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Parameter Min Refresh cycle time /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low Delay time, /RAS high to data Delay time, /CAS high to data Delay time, /OE high to data Transition time 30 9 10 -5 8 5 5 0 3 8 -5 -5 13 18 18 1 -5 Max 64
(Note16)
-6 Min 40 9 10 -5 10 7 5 0 5 10 -5 -5 15 20 20 1 Max 64 40
Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
32
(Note17) (Note18)
20 10
25 13
(Note19) (Note19) (Note20) (Note20) (Note20) (Note21)
50
50
Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 17: tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max).
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 6 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Limits Parameter -5 Min 84 50 8 30 18 0 0 -5 30 13 18 13 Max 10000 10000 Min 104 60 10 35 20 0 0 -5 35 18 20 15 -6 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Read and Refresh Cycles
Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH
Read cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read Setup time after /CAS high Read hold time after /CAS low Read hold time after /RAS low Column address to /RAS hold time Column address to /CAS hold time /RAS hold time after /OE low /CAS hold time after /OE low
(Note 22) (Note 22)
Note 22: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter Write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Write setup time before /CAS low Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after /W low Write pulse width Data setup time before /CAS low or /W low Data hold time after /CAS low or /W low Min 84 50 8 30 18 0 8 8 13 8 -5 13 -5 Max 10000 10000 Min 104 60 10 35 20 0 10 10 15 10 -5 15 -6 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns Unit
(Note 24)
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Parameter Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low /OE hold time after /W low
(Note23)
-5 Min 109 75 38 65 43 0 28 60 40 13 Max 10000 10000 Min 133 89 44 77 49 0 32 72 47 15
-6 Max 10000 10000
Unit ns ns ns ns ns ns ns ns ns ns
(Note24) (Note24) (Note24)
Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min) and tCPWD tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeterminate.
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 7 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Limits
Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle, Read Write Mix Cycle,Hi-Z control by /OE or /W) (Note 25)
Symbol tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
-5 Min 20 55 10 65 8 33 43 7 7 7 28 40 43 13 25 28 Max
Output hold time from /CAS low /RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time, /CAS precharge to W low
Hold time to maintain the data Hi-Z until /CAS access
(Note26) (Note27) (Note24)
100000 13
-6 Min Max 25 66 10 77 100000 10 16 38 50 7 7 7 32 47 50 15 30 33
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
/OE Pulse width (Hi-Z control) /W Pulse width (Hi-Z control) Delay time, /CAS low to /W low after read Delay time, Address to /W low after read Delay time, /CAS precharge to /W low after read Delay time, /CAS low to /OE high after read Delay time, Address to /OE high after read Delay time, /CAS precharge to /OE high after read
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tRAS(min) is specified as two cycles of /CAS input are performed. 27: tCP(max) is specified as a reference point only. If tCP tCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 28)
Limits Symbol tCSR tCHR tRSR tRHR Parameter /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low Min 10 5 15 5 -5 Max Min 10 5 15 5 -6 Max ns ns ns ns Unit
Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode.
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 8 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
(Note 29)
Timing Diagrams Read Cycle
tRC tRAS VIH /RAS VIL tCSH tCRP VIH /CAS VIL tRAD tASR A0~A12,B0 VIH VIL tRAH tASC tCAH
ROW ADDRESS
tRP
tRCD
tRSH tCAS
tCRP
tRAL tCAL
tASR
ROW ADDRESS
COLUMN ADDRESS
tRCS VIH /W VIL tDZC VIH Hi-Z VIL tCAC tAA tCLZ
DQ (OUTPUTS)
tRRH tRCH
tCDD tRDD
DQ (INPUTS)
tREZ tOHR
DATA VALID
tWEZ tOFF tOHC
VOH Hi-Z VOL tRAC tDZO VIH tOEA tOCH tOEZ tODD Hi-Z
/OE VIL tORH
Note 29
Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) VIN VIL(max) Indicates the invalid output.
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 9 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Early Write Cycle
tWC tRAS VIH VIL tCSH tCRP VIH /CAS VIL tASR VIH VIL tASR tRAH tASC tCAH
COLUMN ADDRESS ROW ADDRESS
tRP
/RAS
tRCD
tRSH tCAS
tCRP
A0~A12,B0
ROW ADDRESS
tWCS /W VIH VIL tDS VIH VIL
tWCH
tDH
DQ (INPUTS)
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL
VIH /OE VIL
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 10 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Delayed Write Cycle
tWC tRAS VIH VIL tCSH tCRP VIH / CAS VIL tASR tRAH tASC tCAH tASR
COLUMN ADDRESS ROW ADDRESS
tRP
/RAS
tCRP tRSH tCAS
tRCD
VIH A0~A12,B0 VIL
ROW ADDRESS
tCWL tRCS /W VIH VIL tWCH tDZC
DQ (INPUTS)
tRWL tWP
tDS Hi-Z tCLZ
tDH
DATA VALID
VIH VIL
DQ (OUTPUTS)
VOH Hi-Z VOL tDZO tOEZ tODD tOEH Hi-Z
/OE
VIH VIL
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 11 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tCRP tRP
VIH A0~A12,B0 VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL
tAWD tCWD tRWD
tCWL tRWL tWP
/W
tDS tDZC
DQ (INPUTS)
tDH
VIH VIL tCAC tAA tCLZ
Hi-Z
DATA VALID
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA
DATA VALID
Hi-Z tODD tOEH tOEZ
/OE
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 12 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle
tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tRAD tASR VIH A0~A12,B0 VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL VIH /W VIL tDZC tCAL tCAL
tRRH tRCH
tWEZ tRDD tCDD tCAC tAA tCLZ Hi-Z tCAC tAA tDOH
DATA VALID-1 DATA VALID-2
DQ (INPUTS)
VIH VIL tCAC tAA tDOH tREZ tOHR tOFF tOHC
DATA VALID-3
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL
tCPA tOEA tOCH
tCPA tOEZ
/OE
VIH tODD
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 13 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Early Write Cycle
tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tCAL tASR VIH A0~A12,B0 VIL tRAH tASC tCAH tASC tCAH tASC tCAL tCAH tRCD tCAS tCP tHPC tCAS tRSH tCP tCAS
tRP
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tWCS VIH /W VIL tDS
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
tDS
tDH
tDS
tDH
DQ (INPUTS)
VIH VIL
DATA VALID-1
DATA VALID-2
DATA VALID-3
DQ (OUTPUTS)
VOH Hi-Z VOL
VIL /OE VIH
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 14 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read-Write,Read-Modify-Write Cycle
tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP tHPRWC tCAS
tRP
tRWL tCRP
tASR
ROW ADDRESS
VIH A0~A12,B0 VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tAWD tRCS VIH /W VIL tRWD tDZC
DQ (INPUTS)
tAWD tCWL tWP tRCS tCWD tWP
tCWD
tCPWD tDS tDH
DATA VALID-1
tDZC tDS Hi-Z tCAC tAA tCLZ
tDH
DATA VALID-2
VIH VIL Hi-Z tCAC tAA tCLZ
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIH tOEA
DATA VALID-1
Hi-Z tODD tOEZ tCPA tDZO tOEA
DATA VALID-2
Hi-Z tODD tOEH tOEZ
/OE
VIL
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 15 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
tRAS VIH VIL tCSH tCRP tRCD VIH / CAS VIL tRAD tASR VIH A0~A12,B0 VIL tRAH tASC tCAH tASC tCAH tASC tCAH tCAS tCP tHPC tCAS tCP tHPRWC tCAS tCWL tRWL
tRP
/RAS
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL /W VIH VIL tDZC
tWCS
tWCH tCAL
tCPWD tAWD tCWD tWP
tDS
tDH
tDZ
C
tDS
tDH
DQ (INPUTS)
VIH VIL tCAC tAA tCLZ
DATA VALID-2
DATA VALID-3
tAA tCAC tWEZ
DATA VALID-1
tCLZ
DATA VALID-3
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL
tCPA tOEA tOEZ tOCH tDZO tOEA tOEZ tOEH
/OE
VIH tODD tODD
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 16 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (2)
VIH /RAS VIL tHPC VIH / CAS VIL tCP tASC A0~A12,B0 VIH
COLUMN-1 COLUMN-2 COLUMN-3
tCAS tCAH tASC
tCAS tCAH tASC tCAH
VIL tCAL tRCH tWCS VIH /W VIL tHAWD tHPWD
DQ (INPUTS)
tCAL tWCH
tHCWD tDH tDS
DATA VALID-2
tDZC
VIH Hi-Z VIL tCAC tAA tCPA tWEZ
tCAC tAA tCPA tCLZ
Hi-Z
DQ (OUTPUTS)
VOH VOL tHCOD tHAOD VIL tHPOD
DATA VALID-1
Hi-Z tOEA
DATA VALID-3
tOEZ tODD
tDZC
/OE
VIH
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 17 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by OE )
tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
tCRP
tASR
A0~A12,B0
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRAL tRCS
tRRH tRCH
VIH /W VIL tWEZ tDZC tRDD tCDD tCAC tAA tCLZ
DQ (OUTPUTS)
DQ (INPUTS)
VIH VIL tCAC tAA tDOH
DATA VALID-1 DATA VALID-1 DATA VALID-2
Hi-Z
tCAC tAA tCLZ Hi-Z tCPA
tREZ tOHR tOFF tOHC
DATA VALID-3
VOH Hi-Z VOL tRAC tDZO VIL tOEA
tOEZ tOCH tOEA
tCPA tCHOL
tOEZ
tOEZ
/OE
VIH tOEPE tOEPE tODD
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 18 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Read Cycle ( Hi-Z control by W )
tRAS VIH VIL tCSH tCRP VIH / CAS VIL tRAD tASR VIH A0~A12,B0 VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
/RAS
tCRP
tASR
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRAL tRCS VIH VIL tDZC tWPE tRCH tRCS /W
tRRH tRCH
tRDD tCDD tCAC tAA
DQ (INPUTS)
VIH VIL tCAC tAA tCLZ tCAC tAA tDOH
DATA VALID-1
Hi-Z
tWEZ
DATA VALID-2
tCLZ Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
DQ (OUTPUTS)
VOH Hi-Z VOL tRAC tDZO VIL tOEA tOCH
tCPA
tCPA tOEZ
/OE
VIH tODD
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 19 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
/CAS before /RAS Refresh Cycle
tRC /RAS VIH VIL tRPC tCSR VIH VIL tCPN tCHR tRP tRAS tRAS
tRC tRP
/ CAS
tRPC
tCSR
tCHR
tRPC
tCRP
tASR A0~A12,B0 VIH VIL tRRH /W VIH VIL tRCH tRCS
ROW ADDRESS COLUMN ADDRESS
DQ (INPUTS)
VIH VIL tREZ tOHR tOFF tOHC Hi-Z
DQ (OUTPUTS)
VOH VOL tOEZ VIH
/OE VIL
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 20 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
(Note 31)
Hidden Refresh Cycle (Read)
tRC tRAS /RAS VIH VIL tCRP VIH / CAS VIL tRAD tASR A0~A12,B0 VIH VIL tRCS tRAL tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
tRRH tRCH
/W
VIH VIL tDZC tCDD tRDD
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ Hi-Z VOL tRAC tDZO VIH tOEA tORH tOEZ tODD
DATA VALID
tREZ tOHR tOFF tOHC Hi-Z
DQ (OUTPUTS)
VOH
/OE
VIL
Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 21 / 23 )
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Unit:mm
Package outline
133.35 3.0 127.35
2-o2.0
4.0MA X
31.75 17.78 3.0
4.0
2.0
2-o3.0
2.0 6.35 29x1.27=36.83 6.35 43x1.27=54.61
1.27
8.89 23.50
9x1.27=11.43 43.18
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 22 / 23 )
4.0 3.0 17.78
9/Nov. /1998
Preliminary Spec.
Specifications subject to change without notice.
MITSUBISHI LSIs
MH8V725BAZTJ -5, -6
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MIT-DS-0285-0.0
MITSUBISHI ELECTRIC
( 23 / 23 )
9/Nov. /1998

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